3D DRAM material bottleneck breakthrough! Belgian Realization 120 Layer Si / SiGe Layer

Belgian imec (Belgian Microelectronic Research Center) and Ghent University announced that the successful epitaxial growth of 120-layer Si/SiGe layer structure on a 300 mm silicon wafer is an important breakthrough in promoting 3D DRAM.

The paper was published in Journal of Applied Physics. The traditional DRAM process is reduced to below 10 nanometers, and the capacitance is constantly shrinking, which leads to more difficult charge storage and increased leakage problems. The industry generally believes that the plane slight shrinkage is approaching the extreme limit. To meet the memory needs of AI and high-performance computing (HPC), it is necessary to increase density in the future by "vertical stacking". The concept is similar to the GAA of logical chips, and 3D structure design breaks through existing limitations.

Although HBM (high-frequency wide memory) is often called 3D memory, it is strictly referred to as chip stacking DRAM: firstly manufacturing multiple 2D DRAM grains, then combining them with TSV (silicon perforation), it is still 2D in essence.

The real 3D DRAM is like 3D NAND Flash, where the memory cells are stacked vertically in a single chip in the Z axis direction.

In the past, due to the mismatch between silicon and silicone (SiGe) lattices, defects are prone to occur once there are too many layers, which is difficult to break through the dozens of bottles. This time, the imec team added carbon elements, like a layer of "intact adhesive" between the layer, effectively relieving stress and showing stability.

The

team pointed out that the results proved that the 3D DRAM material level was feasible. Force control and process optimization are gradually maturing, and 3D DRAM is expected to be commercialized like 3D NAND, making AI and data center capacity and energy efficiency higher.

Next-generation 3D DRAM approaches reality as scientists achieve 120-layer stack using advanced deposition techniques